System Levels for Printed Electronics
by Andreas Schaller and Markus Riester
Applying the Hierarchy see : System Hierarchy in Printed Electronics and Costs of Printed RFID's
In the last decades different approaches have been undertaken to define system levels for an electronic system based on Surface Mount Technology (SMT) or through-hole technology (THT). The segmentation of the value chain has benefits for the contributors to the system, as predefined interconnects allow rapid innovation within a levels as long as the interconnects to the neighboring levels are respected. This also allows the segmentation of the value chain to provide materials and technologies optimized for application within the levels. It will be worthwhile exploring the opportunities of this renowned principle in Printed electronics technology.
One of the standard interconnect hierarchy approaches is shown in the figure 1 [Ref: Groover, M., Fundamentals of modern manufacturing). An alternative approach is described in (Ref: Fjelstad, J., Electronic Interconnections No. 10 - The Jisso International Council, 2006, http://www.pcb007.com/pages/zone.cgi?a=7609&z=145&v= , viewed on March 19, 2010).
The system levels start at level 0 (silicon) and continues with Packaging as level 1. On level 2 the printed wiring board (PWB) manufacturing and board assembly takes place. Level 3 stands for the interconnections between different PWB’s, level 4 for the assembly of the PWB into racks, housings of product etc. Finally level 5 represents the connection of several individual products or systems.
Figure 1: SMT System Hierarchy
For allowing Printed Electronics to evolve along the lines of the proven interconnect hierarchy a segmentation of integration levels that can specifically applied to printed electronics is deemed feasible. Printed Electronics technology is meanwhile capable of printing small systems with several functions, i.e. evolving from simple components to more complex integrated systems. Therefore a foundation for the allowing the interconnect structure of the product to be defined and implemented in its electrical design and design for manufacturing will become vital for the further evolution of the technology. It is therefore proposed that such a hierarchy is created. As a starting point the interconnect hierarchy known from the “standard electronics” industry is adopted and modified accordingly.
The Printed electronics Interconnect Hierarchy
In figure 2 a possible version of a Printed electronics Interconnect hierarchy is described.
Like silicon drives the SMT hierarchy in level 0 leveraging its materials driven added value, materials like organic and inorganic nanoinks create the basis for PET system functionality. These functionalities are used for lighting in OLEDs, energy harvesting in OPV,. piezo/pyro effects for printed sensors or simply creating conductive structures for printed antennas.
Level 1, the package/packaging level, can be characterized by functional layers. The layers can be printed on a coated paper, plastic or metal foil. In case of a conductor, e.g. printed antenna this could be a single printed layer with just a single functionality. For printed sensors three or more (structured) layers can be assigned to system layer 1. In other buildups ,e.g. for OLEDs and OPVs the number of printed layers can be much higher.
In many cases it will be desirable to combine different stacks of printed layers, e.g. by lamination, to form a system-in-foil. Typical examples for Level 2 interconnects are printed antennas on a first substrate and logic on a second substrate. Another representation would be printed front and back panel for displays. The foils may also be based on different technology, and also could include non-printed technologies like embedded or mounted IC or SMT components. The functional units on level 2 can be individually tested.
Level 3 in the SMT hierarchy stands for the connections of multiple assembled printed wired boards. For printed electronics this layer represents the linkage of system in foils. The individual functional foils are pretested to account for yield. Typical examples include printed batteries or printed displays connected with other foils to provide power and vision to an existing printed system design.
One primary feature of printed electronic technology solutions is their flexibility. Thus they can be easily integrated into different objects. Mounting or integrating such a printed electronic assembly into a smart system on or into a housing, frame, package or other object is level 4 in the PET system hierarchy.
Finally, a system only becomes smart if it is connected to the rest of the world. In smart packaging scenarios this can be achieved with wireless RF connections, or via a display giving optical response (other modes of communication are of course conceivable ). On level OPVs or OLEDs, are connected to the power grid or lighting systems. For any application level 5 has to be reached as this represents the system layer that integrates the functional product with its surroundings.